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Si5023-EVB
V SLICE = --------------------------------------------
V LOS = ---------------------------------------
prematurely, there is hysterisis in returning from the out-
of-lock condition. LOL will be de-asserted when the
frequency difference is less than ±300 ppm.
LOL is wired to a test point which is located on the
upper right-hand side of the evaluation board.
Loss-of-Signal Alarm Threshold Control
The loss-of-signal alarm (LOS) is used to signal low
incoming data amplitude levels. The input signal to the
threshold control is set by applying a dc voltage level to
the LOS_LVL pin. LOS_LVL is controllable through the
BNC jack J10. The mapping of the LOS_LVL voltage to
The LOS Threshold to LOS Level is mapped as follows:
V LOS_LVL – 1.5
25
If this function is not used, install jumper to JP1 header.
40 mV
30 mV
15 mV
Data Slicing Level
The slicing level allows optimization of the input cross-
over point for systems where the slicing level is not at
the amplitude average. The data slicing level can be
adjusted from the nominal cross-over point of the data
by applying a voltage to the SLICE_LVL pin.
SLICE_LVL is controllable through the BNC jack, J11.
The SLICE_LVL to the data slicing level is mapped as
follows:
V SLICE_LVL – 1.5
50
If this function is not used, jumper JP6.
Bit-Error-Rate Alarm Threshold
The bit-error-rate of the incoming data can be monitored
by the BER_ALM pin. When the bit-error-rate exceeds
an externally-set threshold level, BER_ALM is asserted.
BER_ALM is brought to a test point located in the upper
right-hand corner of the board. The BER_ALM threshold
level is set by applying a dc voltage to the BER_LVL pin.
BER_LVL is controllable through the BNC jack, J12.
Jumper JP7 to disable the BER alarm. Refer to the
“BER Detection” section of the Si5022/Si5023 data
sheet for threshold level programming. The BER_MON
signal (JP14) is reserved for factory testing purposes.
40 mV/V
Test Configuration
0 mV
0V
The three critical jitter tests typically performed on a
CDR device are jitter transfer, jitter tolerance, and jitter
1.00 V
1.50 V
1.875 V
2.25 V
2.5 V
generation. By connecting the Si5023 Evaluation Board
LOS_LVL (V)
Figure 2. LOS_LVL Mapping
Extended LOS Hysteresis Option
An optional LOS Hysteresis Extension circuit is included
on the Si5023-EVB to provide a convenient means of
increasing the amount of LOS Alarm hysteresis when
testing and evaluating the Si5023 LOS functionality.
This simple network will extend the LOS hysteresis to
approximately 6 dB, thereby preventing unnecessary
switching on LOS for low level DATAIN signals in the
range of 20 mV PPD . Hysteresis is defined as the ratio of
the LOS deassert level (LOSD) and the LOS assert
level (LOSA). The hysteresis in decibels is calculated as
20log(LOSD/LOSA). This circuit is constructed with one
CMOS inverter (U2) and two resistors (R12, R13)
mounted on the underside of the PCB. If desired, this
circuit can be enabled by installing a jumper on JP17
(HYST ENABLE) located near the power entry block.
as shown in Figure 3, all three measurements can be
easily made.
When applied, REFCLK should be within ±100 PM of
the frequency selected from Table 1. RATESEL must be
configured to match the desired data rate, and
PWRDN/CAL must be unjumpered.
Jitter Tolerance : Referring to Figure 3, this test
requires a pattern generator, a clock source
(synthesizer signal source), a modulation source, a jitter
analyzer, a pattern analyzer, and a pulse generator (all
unconnected high-speed outputs must be terminated to
50 ? ). During this test, the Jitter Analyzer directs the
Modulation Source to apply prescribed amounts of jitter
to the synthesizer source. This “jitters” the pattern
generator timebase which drives the DATAIN ports of
the CDR. The Bit-Error-Rate (BER) is monitored on the
Pattern Analyzer. The modulation (jitter) frequency and
amplitude is recorded when the BER approaches a
specified threshold. The Si5023 limiting amplifier can
also be examined during this test. Simply lower the
amplitude of the incoming data to the minimum value
Rev. 1.1
3
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